Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductor of an interconnect structure due to metal ion movement caused by the high density of current flow.
Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction of the bottom of the interconnect, which eventually results in a circuit dead opening.
FIGS. 1A-1D are pictorial representations of a prior art interconnect structure at various stages of EM failure. In these drawings, reference numeral 12 denotes the dielectric cap, and reference numeral 10 denotes the conductive feature typically comprised of Cu or some other conductive metal; all other components of the prior art interconnect structure are not labeled to avoid obscuring the EM problem. FIG. 1A is at an initial stress stage. FIG. 1B is at a time when void 14 nucleation initiates at the conductive feature 10/dielectric cap 12 interface. FIG. 1C is at a time when the void 14 grows toward the bottom of the conductive feature 10, and FIG. 1D is at a time in which the void 14 growth crosses the conductive feature 10 causing a circuit dead opening.
In the prior art, two types of capping layers are used for protecting the conductive features of an interconnect structure. One type of capping layer includes a dielectric capping material, while the other type of capping layer includes a metallic capping material. Although both types of capping layers are available, the metallic capping layer typically has better (i.e., increased) adhesion strength to the underlying conductive feature as compared to that obtained using a dielectric capping layer.
The increased adhesion strength provided at the conductive feature/metallic capping layer interface results in improved EM resistance as compared to cases when a dielectric capping layer is employed. For example, the selective deposition of a Co alloy on a conductive feature comprised of Cu has been demonstrated to have a greater than 10 times EM resistance than an interconnect structure including a standard dielectric capping layer.
Despite providing better adhesion and increased EM resistance, prior art metallic capping layers can be attacked or removed (either partially or completely) during a subsequent etching process used in forming an upper interconnect level of an interconnect structure. For example, CoWP metallic capping layers may be damaged or removed (partially or completely) by a subsequent etching step using dilute hydrofluoric acid (DHF) as a chemical etchant.
The attack or removal (partial or complete) of the metallic capping layer in an interconnect structure is undesirable in that it leads to increased EM within the interconnect structure. It is observed that the removal of prior art metallic capping layers is in both the lateral direction and the vertical direction.
In view of the drawbacks mentioned above with prior interconnect structures, there is a need for providing improved interconnect structures in which EM is reduced or completely eliminated. Moreover, there is a need for providing an interconnect structure in which a new and improved metal capping layer is employed which avoids the problems mentioned above with conventional metallic capping layers.